Tokunology合同会社

商号	Tokunology合同会社
英文表記	Tokunology Limited Liability Company
設立	2019年4月1日
所在地	〒965-0878 福島県会津若松市中町1番9号
資本金	200,000円
代表者	代表社員德納弘和
従業員数	1名

事業内容/Field of Activities

コンピュータのソフトウェア及びハードウェアの企画、研究、開発、設計並びにこれらに関するコンサルティング業務
Planning, Research, Design, Development and Consulting for computer software and hardware.
コンピュータの操作指導等に関する事業
Instruction and Training for computer and programming.

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創業者/Founder

TOKUNOU Hirokazu works at manufacturing site to develop applications used inside organization. He has spent most of his career in manufacturing technologies at Japan, U.K. and U.S.

IT Technologies Java/Spring MVC/JUnit, Pentaho ETL, SQL, JavaScript/jQuery, Perl/Mojolicious, Shell, VBA, Arduino…
Non-IT Technologies Statistic Process Control, Desing of Experiment
Preferred Minimum Coding Pentaho ETL, Oracle APEX, Mojolicious, Meteor
Motto Do or Not do. not can nor cann’t.

He is exploring the way to pass better world to next generation using technologies.

德納弘和 (とくのうひろかず)
某社の工場のITシステム部門
39才にして IT部門へ移動
遅れを取り戻すべく日夜勉強中
少し覚えた言語：VBA, SQL, JavaScript, Java, Perl, Shell…
コードを極力書かないのがお気に入り：Pentaho ETL, Oracle APEX, Mojolicious, Meteor
座右の銘：出来る出来へんやない、やるかやらんのかや
個人としてITを活用した社会貢献を模索している。

Github hitokuno

Twitter ochokurin

Slideshare Hirokazu Tokuno

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Cettification

Applied AI with DeepLearning

Patent including Joint invention

JP-H0697184-A: 半導体装置の製造方法
JP-H0786602-A: Manufacture of thin-film transistor
JP-H05251458-A: 半導体装置の製造方法
JP-H07245301-A: Manufacture of semiconductor device
WO-2007050279-A1: Masque dur antireflet a triple couche
US-7220643-B1: System and method for gate formation in a semiconductor device
US-2006214218-A1: Semiconductor device and method of fabricating the same
US-8048797-B2: Multilayer low reflectivity hard mask and process therefor
US-2008108193-A1: Cu annealing for improved data retention in flash memory devices
US-7888269-B2: Triple layer anti-reflective hard mask
US-6464737-B1: Production method and system for granulating powdered material
US-8367493-B1: Void free interlayer dielectric
US-2010009536-A1: Multilayer low reflectivity hard mask and process therefor
US-6833581-B1: Structure and method for preventing process-induced UV radiation damage in a memory cell
US-7884030-B1: Gap-filling with uniform properties
US-8614475-B2: Void free interlayer dielectric
US-2013140720-A1: Void free interlayer dielectric
US-7927723-B1: Film stacks to prevent UV-induced device damage
US-2007029604-A1: Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi-bit memory devices
US-6894342-B1: Structure and method for preventing UV radiation damage in a memory cell and improving contact CD control
US-2007093070-A1: Triple layer anti-reflective hard mask
US-2008096364-A1: Conformal liner for gap-filling
US-7341956-B1: Disposable hard mask for forming bit lines
US-2012045888-A1: Multilayer low reflectivity hard mask and process therefor
US-7534732-B1: Semiconductor devices with copper interconnects and composite silicon nitride capping layers
US-8026169-B2: Cu annealing for improved data retention in flash memory devices
US-8415256-B1: Gap-filling with uniform properties
US-7307027-B1: Void free interlayer dielectric
US-7157335-B1: Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices
US-7538026-B1: Multilayer low reflectivity hard mask and process therefor
US-8309457-B2: Multilayer low reflectivity hard mask and process therefor
US-7238571-B1: Non-volatile memory device with increased reliability